Conductive Anodic Filament (CAF) is one of the most difficult PCB failure mechanisms to diagnose in multilayer PCBs because it develops silently. There’s no cracked joint, no visible burn mark, and often no immediate failure during testing. Instead, CAF forms inside the board over time and reveals itself months later as an intermittent fault or a sudden short in the field.
For products expected to operate for years in electrically biased, humid, or temperature-cycling environments, CAF is not a theoretical concern. It’s a reliability risk that must be addressed early in design and fabrication planning.
This article explains what CAF is, why it forms, and the practical design decisions engineers can use to reduce the risk before boards ever reach production.
What Is Conductive Anodic Filament (CAF)?
CAF is an internal conductive path that develops between copper features inside a multilayer PCB. These paths typically grow along the glass fibers within the laminate, connecting conductors that should remain electrically isolated.
This risk becomes more pronounced as PCB manufacturing pushes toward higher layer counts and tighter spacing.
The mechanism is driven by three conditions working together:
Electrical bias between conductors
Moisture within the laminate
A vulnerable material or structural path, often along the glass weave
Over time, copper ions migrate from the anode toward the cathode and deposit along this path. Once the filament becomes conductive enough, it can cause leakage current or a hard short.
The result is often puzzling behavior: boards that pass initial tests, operate normally in controlled environments, but fail after extended use in humid or voltage-stressed conditions.
Why CAF Forms Inside the Board
CAF is an electrochemical process, not a surface defect. When moisture is present inside the PCB and a voltage exists between conductors, copper ions dissolve and migrate through the resin system. The glass fiber bundles act as preferential pathways, especially if drilling, lamination, or resin bonding leaves micro-voids.
Higher voltage gradients, tighter spacing, and prolonged exposure to humidity accelerate this process. That’s why CAF failures are more common in long-life products, dense multilayer designs, and applications exposed to temperature and moisture cycling.
Design Practices That Reduce CAF Risk
CAF prevention in multilayer PCB starts at the design stage. Treat it as a layout constraint, not as a manufacturing afterthought. The following practices help slow or eliminate filament growth by disrupting the conditions CAF depends on.
1. Increase Conductor Spacing on Inner Layers
Inner layers are more susceptible to CAF because moisture can remain trapped in the laminate. Increasing spacing between conductors at different potentials lengthens the ion migration path and reduces electric field strength.
This is especially important in high-layer-count boards produced through modern PCB manufacturing processes, where internal spacing margins are already compressed.
Pay special attention to:
Via-to-via spacing
Via barrels near plane cutouts
High-bias nets on internal layers
Where possible, exceed the minimum fabrication spacing, especially in designs intended for long service life.
2. Remove Unused Pads and Copper Islands on Inner Layers
Orphan pads and unused copper features on inner layers create stress concentrations and moisture traps. These areas can become initiation points for CAF.
If pads are not electrically required:
Remove them entirely
Replace large copper islands with minimal drill support features per fabrication guidance
Cleaner inner layers reduce both mechanical stress and moisture retention.
3. Avoid Straight-Line Copper Paths Between Opposite Potentials
When conductors of different potentials align directly across layers, they can unintentionally follow the same glass weave path. Offsetting vias and traces often at an angle rather than in straight lines breaks these continuous pathways.
This simple geometric change can significantly reduce the likelihood of electrochemical migration along the laminate structure.
4. Plan Via Placement With Electrical Bias in Mind
Dense via placement is common in modern designs, but opposing-potential vias should not run in long parallel rows across the same dielectric.
Best practices include:
Increasing spacing between high-voltage vias
Offsetting vias instead of aligning them vertically
Applying stricter drill-to-copper clearances in humidity-exposed regions
Designing vias with CAF in mind is especially important for multilayer and HDI boards.
5. Break Up Dense Via Clusters
Large via arrays can create micro-crack stress zones during drilling and lamination. They also encourage moisture movement through capillary paths.
If density is unavoidable, such as under BGAs:
Fan out in stages
Introduce copper voids or keepout channels
Avoid continuous copper adjacency between nets at different potentials
These steps reduce both mechanical stress and moisture pathways.
6. Use Teardrops at Pad and Via Transitions
Teardrops smooth the transition between traces and pads or vias, reducing stress concentration during drilling and thermal cycling.
By minimizing micro-cracks and resin separation at these junctions, teardrops help eliminate the small defects that often act as starting points for CAF growth.
CAF Is a Reliability Issue, Not a Manufacturing Surprise
CAF rarely results from a single mistake. It is usually the outcome of marginal spacing, dense geometry, moisture exposure, and long-term electrical bias acting together. That’s why it must be addressed during design review, material selection, and fabrication planning—not after a failure report arrives.
For products with demanding reliability requirements, CAF mitigation should be part of the standard design checklist alongside creepage, clearance, and impedance control.
For complex multilayer PCB manufacturing, these checks are as critical as material selection and stack-up symmetry.
How PCB Power Supports CAF-Resistant Builds
PCB Power works with manufacturing partners and engineering teams to reduce CAF risk through a combination of design guidance and disciplined PCB manufacturing practices.
PCB Power works with manufacturing partners to reduce CAF risk through a combination of design review and disciplined fabrication practices. This includes:
Advising on laminate and resin systems suitable for long-life applications
Reviewing stack-ups and inner-layer spacing for CAF risk
Controlling drilling and lamination processes to reduce micro-damage
Supporting consistent fabrication practices that improve long-term stability
The objective is straightforward: boards that remain electrically stable throughout their intended service life, not products that fail quietly months after deployment.
If your application demands long-term reliability under voltage and environmental stress, CAF prevention should be addressed early.
Contact PCB Power to discuss your design requirements and fabrication considerations, and align your build.
Frequently Asked Questions
1. What makes CAF difficult to detect during testing?
CAF develops internally and often takes time to become conductive. Boards may pass initial electrical tests and fail only after prolonged exposure to humidity and bias.
2. Is CAF only a concern for high-voltage designs?
No. While higher voltage accelerates CAF, long-life products operating at moderate voltages in humid environments are also at risk.
3. Can material selection reduce CAF risk?
Yes. Resin systems with stronger glass bonding and lower moisture absorption reduce the likelihood of ion migration.
4. Are tighter spacing rules always better?
No. Tighter spacing increases electric field strength and migration risk. Strategic spacing on inner layers is often more effective than pushing minimums.
5. When should CAF be addressed in a project?
During layout and stack-up planning. CAF prevention is most effective before fabrication begins.
